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4-1 semiconductor march 1997 82c54 cmos programmable interval timer features ? 8mhz to 12mhz clock input frequency ? compatible with nmos 8254 - enhanced version of nmos 8253 ? three independent 16-bit counters ? six programmable counter modes ? status read back command ? binary or bcd counting ? fully ttl compatible ? single 5v power supply ? low power - iccsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 m a - iccop . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma at 8mhz ? operating temperature ranges - c82c54 . . . . . . . . . . . . . . . . . . . . . . . . . .0 o c to +70 o c - i82c54 . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c - m82c54 . . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c description the harris 82c54 is a high performance cmos programma- ble interval timer manufactured using an advanced 2 micron cmos process. the 82c54 has three independently programmable and functional 16-bit counters, each capable of handling clock input frequencies of up to 8mhz (82c54) or 10mhz (82c54-10) or 12mhz (82c54-12). the high speed and industry standard con?guration of the 82c54 make it compatible with the harris 80c86, 80c88, and 80c286 cmos microprocessors along with many other industry standard processors. six programmable timer modes allow the 82c54 to be used as an event counter, elapsed time indicator, programmable one-shot, and many other applications. static cmos circuit design insures low power operation. the harris advanced cmos process results in a signi?cant reduction in power with performance equal to or greater than existing equivalent products. pinouts 82c54 (pdip, cerdip, soic) top view 82c54 (plcc/clcc) top view 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 d7 d6 d5 d4 d3 d2 d1 d0 clk 0 out 0 gate 0 gnd vcc rd cs a1 a0 out 2 clk 1 gate 1 out 1 wr clk 2 gate 2 gnd nc out 1 gate 1 clk 1 out 0 gate 0 d7 nc vcc wr rd d5 d6 cs a1 a0 clk2 nc gate 2 out 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 d3 d2 d1 d0 d4 nc clk 0 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? harris corporation 1997 file number 2970.1
4-2 functional diagram ordering information part numbers temperature range package pkg. no. 8mhz 10mhz 12mhz cp82c54 cp82c54-10 cp82c54-12 0 o c to +70 o c 24 lead pdip e24.6 ip82c54 ip82c54-10 ip82c54-12 -40 o c to +85 o c 24 lead pdip e24.6 cs82c54 cs82c54-10 cs82c54-12 0 o c to +70 o c 28 lead plcc n28.45 is82c54 is82c54-10 is82c54-12 -40 o c to +85 o c 28 lead plcc n28.45 cd82c54 cd82c54-10 cd82c54-12 0 o c to +70 o c 24 lead cerdip f24.6 id82c54 id82c54-10 id82c54-12 -40 o c to +85 o c 24 lead cerdip f24.6 md82c54/b md82c54-10/b md82c54-12/b -55 o c to +125 o c 24 lead cerdip f24.6 mr82c54/b mr82c54-10/b mr82c54-12/b -55 o c to +125 o c 28 lead clcc j28.a smd # 8406501JA - 8406502ja -55 o c to +125 o c 24 lead cerdip f24.6 smd# 84065013a - 84065023a -55 o c to +125 o c 28 lead clcc j28.a cm82c54 cm82c54-10 cm82c54-12 0 o c to +70 o c 24 lead soic m24.3 pin description symbol dip pin number type definition d7 - d0 1 - 8 i/o data: bi-directional three-state data bus lines, connected to system data bus. clk 0 9 i clock 0: clock input of counter 0. out 0 10 o out 0: output of counter 0. gate 0 11 i gate 0: gate input of counter 0. gnd 12 ground: power supply connection. out 1 13 o out 1: output of counter 1. gate 1 14 i gate 1: gate input of counter 1. clk 1 15 i clock 1: clock input of counter 1. gate 2 16 i gate 2: gate input of counter 2. out 2 17 o out 2: output of counter 2. control word register read/ write logic data/ bus buffer counter 2 counter 1 counter 0 internal bus internal bus control logic control word register status latch status register clk n gate n out n out 2 gate 2 clk 2 out 1 gate 1 clk 1 out 0 gate 0 clk 0 wr rd d 7 - d 0 a 0 a 1 cs ol m ol l ce cr m cr l counter internal block diagram 8 82c54
4-3 functional description general the 82c54 is a programmable interval timer/counter designed for use with microcomputer systems. it is a general purpose, multi-timing element that can be treated as an array of i/o ports in the system software. the 82c54 solves one of the most common problems in any microcomputer system, the generation of accurate time delays under software control. instead of setting up timing loops in software, the programmer con?gures the 82c54 to match his requirements and programs one of the counters for the desired delay. after the desired delay, the 82c54 will interrupt the cpu. software overhead is minimal and vari- able length delays can easily be accommodated. some of the other computer/timer functions common to micro- computers which can be implemented with the 82c54 are: ? real time clock ? event counter ? digital one-shot ? programmable rate generator ? square wave generator ? binary rate multiplier ? complex waveform generator ? complex motor controller data bus buffer this three-state, bi-directional, 8-bit buffer is used to inter- face the 82c54 to the system bus (see figure 1). read/write logic the read/write logic accepts inputs from the system bus and generates control signals for the other functional blocks of the 82c54. a1 and a0 select one of the three counters or the con- trol word register to be read from/written into. a low on the rd input tells the 82c54 that the cpu is reading one of the counters. a low on the wr input tells the 82c54 that the cpu is writing either a control word or an initial count. both rd and wr are quali?ed by cs; rd and wr are ignored unless the 82c54 has been selected by holding cs low. clk 2 18 i clock 2: clock input of counter 2. a0, a1 19 - 20 i address: select inputs for one of the three counters or control word register for read/write operations. normally connected to the system address bus. cs 21 i chip select: a low on this input enables the 82c54 to respond to rd and wr signals. rd and wr are ignored otherwise. rd 22 i read: this input is low during cpu read operations. wr 23 i write: this input is low during cpu write operations. v cc 24 v cc : the +5v power supply pin. a 0.1 m f capacitor between pins vcc and gnd is recommended for decoupling. pin description (continued) symbol dip pin number type definition a1 a0 selects 0 0 counter 0 0 1 counter 1 1 0 counter 2 1 1 control word register control word register counter 2 counter 1 counter 0 internal bus out 2 gate 2 clk 2 out 1 gate 1 clk 1 out 0 gate 0 clk 0 wr rd d 7 - d 0 a 0 a 1 cs figure 1. data bus buffer and read/write logic functions 8 data/ bus buffer read/ write logic 82c54
4-4 control word register the control word register (figure 2) is selected by the read/write logic when a1, a0 = 11. if the cpu then does a write operation to the 82c54, the data is stored in the con- trol word register and is interpreted as a control word used to de?ne the counter operation. the control word register can only be written to; status information is available with the read-back command. counter 0, counter 1, counter 2 these three functional blocks are identical in operation, so only a single counter will be described. the internal block diagram of a signal counter is shown in figure 3. the counters are fully independent. each counter may operate in a different mode. the control word register is shown in the ?gure; it is not part of the counter itself, but its contents determine how the counter operates. the status register, shown in the ?gure, when latched, con- tains the current contents of the control word register and status of the output and null count ?ag. (see detailed expla- nation of the read-back command.) the actual counter is labeled ce (for counting element). it is a 16-bit presettable synchronous down counter. olm and oll are two 8-bit latches. ol stands for output latch; the subscripts m and l for most signi?cant byte and least signi?cant byte, respectively. both are normally referred to as one unit and called just ol. these latches normally fol- low the ce, but if a suitable counter latch command is sent to the 82c54, the latches latch the present count until read by the cpu and then return to following the ce. one latch at a time is enabled by the counters control logic to drive the inter- nal bus. this is how the 16-bit counter communicates over the 8-bit internal bus. note that the ce itself cannot be read; when- ever you read the count, it is the ol that is being read. similarly, there are two 8-bit registers called crm and crl (for count register). both are normally referred to as one unit and called just cr. when a new count is written to the counter, the count is stored in the cr and later transferred to the ce. the control logic allows one register at a time to be loaded from the internal bus. both bytes are transferred to the ce simulta- neously. crm and crl are cleared when the counter is pro- grammed for one byte counts (either most signi?cant byte only or least signi?cant byte only) the other byte will be zero. note that the ce cannot be written into; whenever a count is written, it is written into the cr. the control logic is also shown in the diagram. clk n, gate n, and out n are all connected to the outside world through the control logic. 82c54 system interface the 82c54 is treated by the system software as an array of peripheral i/o ports; three are counters and the fourth is a control register for mode programming. basically, the select inputs a0, a1 connect to the a0, a1 address bus signals of the cpu. the cs can be derived directly from the address bus using a linear select method or it can be connected to the output of a decoder. read/ write logic data/ bus buffer internal bus out 2 gate 2 clk 2 out 1 gate 1 clk 1 out 0 gate 0 clk 0 wr rd d 7 - d 0 a 0 a 1 cs figure 2. control word register and counter functions 8 control word register counter 2 counter 1 counter 0 internal bus control logic control word register status latch status register clk n gate n out n ol m ol l ce cr m cr l figure 3. counter internal block diagram 82c54
4-5 operational description general after power-up, the state of the 82c54 is unde?ned. the mode, count value, and output of all counters are unde?ned. how each counter operates is determined when it is pro- grammed. each counter must be programmed before it can be used. unused counters need not be programmed. programming the 82c54 counters are programmed by writing a control word and then an initial count. all control words are written into the control word register, which is selected when a1, a0 = 11. the control word spec- i?es which counter is being programmed. by contrast, initial counts are written into the counters, not the control word register. the a1, a0 inputs are used to select the counter to be written into. the format of the initial count is determined by the control word used. figure 4. 82c54 system interface write operations the programming procedure for the 82c54 is very ?exible. only two conventions need to be remembered: 1. for each counter, the control word must be written before the initial count is written. 2. the initial count must follow the count format speci?ed in the control word (least signi?cant byte only, most signi?cant byte only, or least signi?cant byte and then most signi?cant byte). since the control word register and the three counters have separate addresses (selected by the a1, a0 inputs), and each control word speci?es the counter it applies to (sc0, sc1 bits), no special instruction sequence is required. any programming sequence that follows the conventions above is acceptable. control word format a1, a0 = 11; cs = 0; rd = 1; wr = 0 d7 d6 d5 d4 d3 d2 d1 d0 sc1 sc0 rw1 rw0 m2 m1 m0 bcd address bus (16) control bus data bus (8) i/or i/o w wr rd cs a0 a1 a1 a0 8 counter 0 out gate clk counter 1 counter 2 out gate clk out gate clk d0 - d7 82c54 sc - select counter sc1 sc0 0 0 select counter 0 0 1 select counter 1 1 0 select counter 2 1 1 read-back command (see read operations) rw - read/write rw1 rw0 0 0 counter latch command (see read operations) 0 1 read/write least significant byte only. 1 0 read/write most significant byte only. 1 1 read/write least significant byte first, then most significant byte. m - mode m2 m1 m0 0 0 0 mode 0 0 0 1 mode 1 x 1 0 mode 2 x 1 1 mode 3 1 0 0 mode 4 1 0 1 mode 5 bcd - binary coded decimal 0 binary counter 16-bit 1 binary coded decimal (bcd) counter (4 decades) note: dont care bits (x) should be 0 to insure compatibility with future products. possible programming sequence a1 a0 control word - counter 0 1 1 lsb of count - counter 0 0 0 msb of count - counter 0 0 0 control word - counter 1 1 1 lsb of count - counter 1 0 1 msb of count - counter 1 0 1 control word - counter 2 1 1 lsb of count - counter 2 1 0 msb of count - counter 2 1 0 possible programming sequence a1 a0 control word - counter 0 1 1 control word - counter 1 1 1 control word - counter 2 1 1 lsb of count - counter 2 1 0 82c54
4-6 a new initial count may be written to a counter at any time without affecting the counters programmed mode in any way. counting will be affected as described in the mode de?nitions. the new count must follow the programmed count format. if a counter is programmed to read/write two-byte counts, the following precaution applies. a program must not transfer control between writing the ?rst and second byte to another routine which also writes into that same counter. otherwise, the counter will be loaded with an incorrect count. read operations it is often desirable to read the value of a counter without disturbing the count in progress. this is easily done in the 82c54. there are three possible methods for reading the counters. the ?rst is through the read-back command, which is explained later. the second is a simple read operation of the counter, which is selected with the a1, a0 inputs. the only requirement is that the clk input of the selected counter must be inhibited by using either the gate input or external logic. otherwise, the count may be in process of changing when it is read, giving an unde?ned result. counter latch command the other method for reading the counters involves a spe- cial software command called the counter latch com- mand. like a control word, this command is written to the control word register, which is selected when a1, a0 = 11. also, like a control word, the sc0, sc1 bits select one of the three counters, but two other bits, d5 and d4, distin- guish this command from a control word. . the selected counters output latch (ol) latches the count when the counter latch command is received. this count is held in the latch until it is read by the cpu (or until the counter is reprogrammed). the count is then unlatched automatically and the ol returns to following the counting element (ce). this allows reading the contents of the counters on the ?y without affecting counting in progress. multiple counter latch commands may be used to latch more than one counter. each latched counters ol holds its count until read. counter latch commands do not affect the programmed mode of the counter in any way. if a counter is latched and then, some time later, latched again before the count is read, the second counter latch command is ignored. the count read will be the count at the time the ?rst counter latch command was issued. with either method, the count must be read according to the programmed format; speci?cally, if the counter is pro- grammed for two byte counts, two bytes must be read. the two bytes do not have to be read one right after the other; read or write or programming operations of other counters may be inserted between them. another feature of the 82c54 is that reads and writes of the same counter may be interleaved; for example, if the counter is programmed for two byte counts, the following sequence is valid. lsb of count - counter 1 0 1 lsb of count - counter 0 0 0 msb of count - counter 0 0 0 msb of count - counter 1 0 1 msb of count - counter 2 1 0 possible programming sequence a1 a0 control word - counter 2 1 1 control word - counter 1 1 1 control word - counter 0 1 1 lsb of count - counter 2 1 0 msb of count - counter 2 1 0 lsb of count - counter 1 0 1 msb of count - counter 1 0 1 lsb of count - counter 0 0 0 msb of count - counter 0 0 0 possible programming sequence a1 a0 control word - counter 1 1 1 control word - counter 0 1 1 lsb of count - counter 1 0 1 control word - counter 2 1 1 lsb of count - counter 0 0 0 msb of count - counter 1 0 1 lsb of count - counter 2 1 0 msb of count - counter 0 0 0 msb of count - counter 2 1 0 note: in all four examples, all counters are programmed to read/write two-byte counts. these are only four of many programming sequences. possible programming sequence (continued) a1 a0 a1, a0 = 11; cs = 0; rd = 1; wr = 0 d7 d6 d5 d4 d3 d2 d1 d0 sc1sc00 0xxxx sc1, sc0 - specify counter to be latched sc1 sc0 counter 00 0 01 1 10 2 1 1 read-back command d5, d4 - 00 designates counter latch command, x - dont care. note: dont care bits (x) should be 0 to insure compatibility with future products. 82c54
4-7 1. read least signi?cant byte. 2. write new least signi?cant byte. 3. read most signi?cant byte. 4. write new most signi?cant byte. if a counter is programmed to read or write two-byte counts, the following precaution applies: a program must not transfer control between reading the ?rst and second byte to another routine which also reads from that same counter. otherwise, an incorrect count will be read. read-back command the read-back command allows the user to check the count value, programmed mode, and current state of the out pin and null count ?ag of the selected counter(s). the command is written into the control word register and has the format shown in figure 5. the command applies to the counters selected by setting their corresponding bits d3, d2, d1 = 1. the read-back command may be used to latch multiple counter output latches (ol) by setting the count bit d5 = 0 and selecting the desired counter(s). this signal command is functionally equivalent to several counter latch commands, one for each counter latched. each counters latched count is held until it is read (or the counter is reprogrammed). that counter is automatically unlatched when read, but other counters remain latched until they are read. if multiple count read-back commands are issued to the same counter with- out reading the count, all but the ?rst are ignored; i.e., the count which will be read is the count at the time the ?rst read-back command was issued. the read-back command may also be used to latch status information of selected counter(s) by setting status bit d4 = 0. status must be latched to be read; status of a counter is accessed by a read from that counter. the counter status format is shown in figure 6. bits d5 through d0 contain the counters programmed mode exactly as written in the last mode control word. output bit d7 contains the current state of the out pin. this allows the user to monitor the counters output via software, possibly eliminating some hardware from a system. null count bit d6 indicates when the last count written to the counter register (cr) has been loaded into the counting element (ce). the exact time this happens depends on the mode of the counter and is described in the mode de?nitions, but until the counter is loaded into the counting element (ce), it cant be read from the counter. if the count is latched or read before this time, the count value will not re?ect the new count just written. the operation of null count is shown below. this action: causes: a. write to the control word register:(1) . . . . . . . . . . null count = 1 b. write to the count register (cr):(2) . . . . . . . . . . . null count = 1 c. new count is loaded into ce (cr - ce) . . . . . . . . null count = 0 (1) only the counter speci?ed by the control word will have its null count set to 1. null count bits of other counters are unaffected. (2) if the counter is programmed for two-byte counts (least signi?- cant byte then most signi?cant byte) null count goes to 1 when the second byte is written. if multiple status latch operations of the counter(s) are per- formed without reading the status, all but the ?rst are ignored; i.e., the status that will be read is the status of the counter at the time the ?rst status read-back command was issued. figure 7. read-back command example a0, a1 = 11; cs = 0; rd = 1; wr = 0 d7 d6 d5 d4 d3 d2 d1 d0 11 count st a tus cnt 2 cnt 1 cnt 0 0 d5: 0 = latch count of selected counter (s) d4: 0 = latch status of selected counter(s) d3: 1 = select counter 2 d2: 1 = select counter 1 d1: 1 = select counter 0 d0: reserved for future expansion; must be 0 figure 5. read-back command format d7 d6 d5 d4 d3 d2 d1 d0 output null count rw1 rw0 m2 m1 m0 bcd d7: 1 = out pin is 1 0 = out pin is 0 d6: 1 = null count 0 = count available for reading d5 - d0 = counter programmed mode (see control word formats) figure 6. status byte commands description result d7 d6 d5 d4 d3 d2 d1 d0 11000010 read-back count and status of counter 0 count and status latched for counter 0 11100100 read-back status of counter 1 status latched for counter 1 11101100 read-back status of counters 2, 1 status latched for counter 2, but not counter 1 11011000 read-back count of counter 2 count latched for counter 2 11000100 read-back count and status of counter 1 count latched for counter 1, but not status 11100010 read-back status of counter 1 command ignored, status already latched for counter 1 82c54
4-8 both count and status of the selected counter(s) may be latched simultaneously by setting both count and status bits d5, d4 = 0. this is functionally the same as issuing two separate read-back commands at once, and the above dis- cussions apply here also. speci?cally, if multiple count and/or status read-back commands are issued to the same counter(s) without any intervening reads, all but the ?rst are ignored. this is illustrated in figure 7. if both count and status of a counter are latched, the ?rst read operation of that counter will return latched status, regardless of which was latched ?rst. the next one or two reads (depending on whether the counter is programmed for one or two type counts) return latched count. subsequent reads return unlatched count. mode de?nitions the following are de?ned for use in describing the operation of the 82c54. clk pulse: a rising edge, then a falling edge, in that order, of a counters clk input. trigger: a rising edge of a counters gate input. counter loading: the transfer of a count from the cr to the ce (see func- tional description) mode 0: interrupt on terminal count mode 0 is typically used for event counting. after the control word is written, out is initially low, and will remain low until the counter reaches zero. out then goes high and remains high until a new count or a new mode 0 control word is writ- ten to the counter. gate = 1 enables counting; gate = 0 disables counting. gate has no effect on out. after the control word and initial count are written to a counter, the initial count will be loaded on the next clk pulse. this clk pulse does not decrement the count, so for an initial count of n, out does not go high until n + 1 clk pulses after the initial count is written. if a new count is written to the counter it will be loaded on the next clk pulse and counting will continue from the new count. if a two-byte count is written, the following happens: (1) writing the ?rst byte disables counting. out is set low immediately (no clock pulse required). (2) writing the second byte allows the new count to be loaded on the next clk pulse. this allows the counting sequence to be synchronized by software. again out does not go high until n + 1 clk pulses after the new count of n is written. if an initial count is written while gate = 0, it will still be loaded on the next clk pulse. when gate goes high, out will go high n clk pulses later; no clk pulse is needed to load the counter as this has already been done. figure 9. mode 0 notes: the following conventions apply to all mode timing diagrams. 1. counters are programmed for binary (not bcd) counting and for reading/writing least signi?cant byte (lsb) only. 2. the counter is always selected ( cs always low). 3. cw stands for control word; cw = 10 means a control word of 10, hex is written to the counter. 4. lsb stands for least significant byte of count. 5. numbers below diagrams are count values. the lower number is the least significant byte. the upper number is the most signifi- cant byte. since the counter is programmed to read/write lsb only, the most significant byte cannot be read. 6. n stands for an undefined count. 7. vertical lines show transitions between count values. cs rd wr a1 a0 01000 write into counter 0 01001 write into counter 1 01010 write into counter 2 01011 write control word 00100 read from counter 0 00101 read from counter 1 00110 read from counter 2 00111 no-operation (three-state) 1xxxx no-operation (three-state) 0 1 1 x x no-operation (three-state) figure 8. read/write operations summary cw = 10 lsb = 4 wr clk gate out wr clk gate out wr clk gate out cw = 10 lsb = 3 cw = 10 lsb = 3 lsb = 2 nnnn 0 4 0 3 0 2 0 1 0 0 ff ff ff fe nnnn 0 3 0 2 0 2 0 2 0 1 0 0 ff ff nnnn 0 3 0 2 0 1 0 2 0 1 0 0 ff ff 82c54
4-9 mode 1: hardware retriggerable one-shot out will be initially high. out will go low on the clk pulse following a trigger to begin the one-shot pulse, and will remain low until the counter reaches zero. out will then go high and remain high until the clk pulse after the next trigger. after writing the control word and initial count, the counter is armed. a trigger results in loading the counter and setting out low on the next clk pulse, thus starting the one-shot pulse n clk cycles in duration. the one-shot is retriggerable, hence out will remain low for n clk pulses after any trigger. the one-shot pulse can be repeated without rewriting the same count into the counter. gate has no effect on out. if a new count is written to the counter during a one-shot pulse, the current one-shot is not affected unless the counter is retriggerable. in that case, the counter is loaded with the new count and the one-shot pulse continues until the new count expires. figure 10. mode 1 mode 2: rate generator this mode functions like a divide-by-n counter. it is typically used to generate a real time clock interrupt. out will ini- tially be high. when the initial count has decremented to 1, out goes low for one clk pulse. out then goes high again, the counter reloads the initial count and the process is repeated. mode 2 is periodic; the same sequence is repeated inde?nitely. for an initial count of n, the sequence repeats every n clk cycles. gate = 1 enables counting; gate = 0 disables counting. if gate goes low during an output pulse, out is set high immediately. a trigger reloads the counter with the initial count on the next clk pulse; out goes low n clk pulses after the trigger. thus the gate input can be used to syn- chronize the counter. after writing a control word and initial count, the counter will be loaded on the next clk pulse. out goes low n clk pulses after the initial count is written. this allows the counter to be synchronized by software also. writing a new count while counting does not affect the current counting sequence. if a trigger is received after writing a new count but before the end of the current period, the counter will be loaded with the new count on the next clk pulse and count- ing will continue from the end of the current counting cycle. figure 11. mode 2 wr clk gate out wr clk gate out wr clk gate out nnnn 0 3 0 2 0 1 0 0 ff ff 0 3 0 2 n cw = 12 lsb = 3 cw = 12 lsb = 3 cw = 12 lsb = 2 lsb = 4 nnnn 0 2 0 1 0 0 ff ff ff fe 0 4 0 3 n nnnn 0 3 0 2 0 1 0 3 0 2 0 1 0 0 n nnnn 0 2 0 1 0 3 0 2 0 1 0 3 0 3 nnnn 0 2 0 2 0 3 0 2 0 1 0 3 0 3 nnnn 0 3 0 2 0 1 0 5 0 4 0 3 0 4 wr clk gate out cw = 14 lsb = 3 wr clk gate out cw = 14 lsb = 3 wr clk gate out cw = 14 lsb = 4 lsb = 5 82c54
4-10 mode 3: square wave mode mode 3 is typically used for baud rate generation. mode 3 is similar to mode 2 except for the duty cycle of out. out will initially be high. when half the initial count has expired, out goes low for the remainder of the count. mode 3 is periodic; the sequence above is repeated inde?nitely. an initial count of n results in a square wave with a period of n clk cycles. gate = 1 enables counting; gate = 0 disables counting. if gate goes low while out is low, out is set high immedi- ately; no clk pulse is required. a trigger reloads the counter with the initial count on the next clk pulse. thus the gate input can be used to synchronize the counter. after writing a control word and initial count, the counter will be loaded on the next clk pulse. this allows the counter to be synchronized by software also. writing a new count while counting does not affect the cur- rent counting sequence. if a trigger is received after writing a new count but before the end of the current half-cycle of the square wave, the counter will be loaded with the new count on the next clk pulse and counting will continue from the new count. otherwise, the new count will be loaded at the end of the current half-cycle. figure 12. mode 3 mode 3 is implemented as follows: even counts: out is initially high. the initial count is loaded on one clk pulse and then is decremented by two on succeeding clk pulses. when the count expires, out changes value and the counter is reloaded with the initial count. the above process is repeated inde?nitely. odd counts: out is initially high. the initial count is loaded on one clk pulse, decremented by one on the next clk pulse, and then decremented by two on succeeding clk pulses. when the count expires, out goes low and the counter is reloaded with the initial count. the count is decremented by three on the next clk pulse, and then by two on succeeding clk pulses. when the count expires, out goes high again and the counter is reloaded with the initial count. the above pro- cess is repeated inde?nitely. so for odd counts, out will be high for (n + 1)/2 counts and low for (n - 1)/2 counts. mode 4: software triggered mode out will be initially high. when the initial count expires, out will go low for one clk pulse then go high again. the count- ing sequence is triggered by writing the initial count. gate = 1 enables counting; gate = 0 disables counting. gate has no effect on out. after writing a control word and initial count, the counter will be loaded on the next clk pulse. this clk pulse does not decre- ment the count, so for an initial count of n, out does not strobe low until n + 1 clk pulses after the initial count is written. if a new count is written during counting, it will be loaded on the next clk pulse and counting will continue from the new count. if a two-byte count is written, the following happens: (1) writing the ?rst byte has no effect on counting. (2) writing the second byte allows the new count to be loaded on the next clk pulse. this allows the sequence to be retriggered by software. out strobes low n + 1 clk pulses after the new count of n is written. nnn n 0 2 0 4 0 2 0 4 0 2 0 4 0 2 0 4 0 4 0 2 nnn n 0 4 0 2 0 5 0 2 0 5 0 4 0 2 0 5 0 5 0 2 nnn n 0 2 0 4 0 2 0 2 0 2 0 4 0 2 0 4 0 4 0 2 wr clk gate out cw = 16 lsb = 4 wr clk gate out wr clk gate out cw = 16 lsb = 5 cw = 16 lsb = 4 82c54
4-11 figure 13. mode 4 mode 5: hardware triggered strobe (retriggerable) out will initially be high. counting is triggered by a rising edge of gate. when the initial count has expired, out will go low for one clk pulse and then go high again. after writing the control word and initial count, the counter will not be loaded until the clk pulse after a trigger. this clk pulse does not decrement the count, so for an initial count of n, out does not strobe low until n + 1 clk pulses after trigger. a trigger results in the counter being loaded with the initial count on the next clk pulse. the counting sequence is trig- gerable. out will not strobe low for n + 1 clk pulses after any trigger gate has no effect on out. if a new count is written during counting, the current count- ing sequence will not be affected. if a trigger occurs after the new count is written but before the current count expires, the counter will be loaded with new count on the next clk pulse and counting will continue from there. figure 14. mode 5 operation common to all modes programming when a control word is written to a counter, all control logic, is immediately reset and out goes to a known initial state; no clk pulses are required for this. gate the gate input is always sampled on the rising edge of clk. in modes 0, 2, 3 and 4 the gate input is level sensi- tive, and logic level is sampled on the rising edge of clk. in modes 1, 2, 3 and 5 the gate input is rising-edge sensitive. in these modes, a rising edge of gate (trigger) sets an edge- sensitive ?ip-?op in the counter. this ?ip-?op is then sam- pled on the next rising edge of clk. the ?ip-?op is reset immediately after it is sampled. in this way, a trigger will be detected no matter when it occurs - a high logic level does not have to be maintained until the next rising edge of clk. note that in modes 2 and 3, the gate input is both edge- and level-sensitive. nnnn 0 2 0 1 0 0 ff ff ff fe ff fd 0 3 wr clk gate out cw = 18 lsb = 3 wr clk gate out wr clk gate out cw = 18 lsb = 3 cw = 18 lsb = 3 nnn 0 3 0 2 0 1 0 2 0 1 0 0 ff ff nn n n 0 3 0 3 0 2 0 1 0 0 ff ff 0 3 lsb = 2 n nnnn 0 3 0 2 0 1 0 0 ff ff 0 3 wr clk gate out cw = 1a lsb = 3 nnnn 0 3 0 2 0 3 0 2 0 1 nnnn 0 3 0 2 0 1 0 0 ff ff ff fe wr clk gate out cw = 1a lsb = 3 wr clk gate out cw = 1a lsb = 3 n nn 0 0 ff ff lsb = 5 n 0 5 0 4 82c54
4-12 counter new counts are loaded and counters are decremented on the falling edge of clk. the largest possible initial count is 0; this is equivalent to 2 16 for binary counting and 10 4 for bcd counting. the counter does not stop when it reaches zero. in modes 0, 1, 4, and 5 the counter wraps around to the highest count, either ffff hex for binary counting or 9999 for bcd count- ing, and continues counting. modes 2 and 3 are periodic; the counter reloads itself with the initial count and continues counting from there. figure 15. gate pin operations summary figure 16. minimum and maximum initial counts signal status modes low or going low rising high 0 disables counting - enables counting 1 - 1) initiates counting 2) resets output after next clock - 2 1) disables counting 2) sets output im- mediately high initiates counting enables counting 3 1) disables counting 2) sets output im- mediately high initiates counting enables counting 4 1) disables counting - enables counting 5 - initiates counting - mode min count max count 010 110 220 320 410 510 note: 0 is equivalent to 2 16 for binary counting and 10 4 for bcd counting. 82c54
4-13 ) absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage . . . . . . . . . . . . gnd-0.5v to v cc +0.5v esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range c82c54, c82c54-10, -12 . . . . . . . . . . . . . . . . . . . . 0 o c to +70 o c i82c54, i82c54-10, -12 . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c m82c54, m82c54-10, -12 . . . . . . . . . . . . . . . . . -55 o c to +125 o c thermal resistance (typical) q ja ( o c/w) q jc ( o c/w) cerdip package . . . . . . . . . . . . . . . . 55 12 clcc package . . . . . . . . . . . . . . . . . . 65 14 pdip package . . . . . . . . . . . . . . . . . . . 60 n/a plcc package . . . . . . . . . . . . . . . . . . 65 n/a soic package . . . . . . . . . . . . . . . . . . . 75 n/a storage temperature range . . . . . . . . . . . . . . . . . .-65 o c to +150 o c maximum junction temperature ceramic package . . . . . . . +175 o c maximum junction temperature plastic package. . . . . . . . . +150 o c maximum lead temperature package (soldering 10s) . . . . +300 o c (plcc and soic - lean tips only) die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2250 gates caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. dc electrical speci?cations v cc = +5.0v 10%, t a = 0 o c to +70 o c (c82c54, c82c54-10, c82c54-12) t a = -40 o c to +85 o c (i82c54, i82c54-10, i82c54-12) t a = -55 o c to +125 o c (m82c54, m82c54-10, m82c54-12 symbol parameter min max units test conditions vih logical one input voltage 2.0 - v c82c54, i82c54 2.2 - v m82c54 vil logical zero input voltage - 0.8 v voh output high voltage 3.0 - v ioh = -2.5ma v cc -0.4 - v ioh = -100 m a vol output low voltage - 0.4 v iol = +2.5ma ii input leakage current -1 +1 m a vin = gnd or v cc dip pins 9,11,14-16,18-23 io output leakage current -10 +10 m a vout = gnd or v cc dip pins 1-8 iccsb standby power supply current - 10 m av cc = 5.5v, vin = gnd or v cc , outputs open, counters programmed iccop operating power supply current - 10 ma v cc = 5.5v, clk0 = clk1 = clk2 = 8mhz, vin = gnd or v cc , outputs open capacitance t a = +25 o c; all measurements referenced to device gnd, note 1 symbol parameter typ units test conditions cin input capacitance 20 pf freq = 1mhz cout output capacitance 20 pf freq = 1mhz ci/o i/o capacitance 20 pf freq = 1mhz note: 1. not tested, but characterized at initial design and at major process/design changes. 82c54
4-14 ac electrical speci?cations v cc = +5.0v 10%, t a = 0 o c to +70 o c (c82c54, c82c54-10, c82c54-12) t a = -40 o c to +85 o c (i82c54, i82c54-10, i82c54-12) t a = -55 o c to +125 o c (m82c54, m82c54-10, m82c54-12) symbol parameter 82c54 82c54-10 82c54-12 units test conditions min max min max min max read cycle (1) tar address stable before rd 30 - 25 - 25 - ns 1 (2) tsr cs stable before rd 0-0-0-ns 1 (3) tra address hold time after rd0-0-0-ns 1 (4) trr rd pulse width 150 - 95 - 95 - ns 1 (5) trd data delay from rd - 120 - 85 - 85 ns 1 (6) tad data delay from address - 210 - 185 - 185 ns 1 (7) tdf rd to data floating 5 85 5 65 5 65 ns 2, note 1 (8) trv command recovery time 200 - 165 - 165 - ns write cycle (9) taw address stable before wr 0-0-0-ns (10) tsw cs stable before wr 0-0-0-ns (11) twa address hold time after wr0-0-0-ns (12) tww wr pulse width 95 - 95 - 95 - ns (13) tdw data setup time before wr 140 - 95 - 95 - ns (14) twd data hold time after wr 25 - 0 - 0 - ns (15) trv command recovery time 200 - 165 - 165 - ns clock and gate (16) tclk clock period 125 dc 100 dc 80 dc ns 1 (17) tpwh high pulse width 60 - 30 - 30 - ns 1 (18) tpwl low pulse width 60 - 40 - 30 - ns 1 (19) tr clock rise time - 25 - 25 - 25 ns (20) tf clock fall time - 25 - 25 - 25 ns (21) tgw gate width high 50 - 50 - 50 - ns 1 (22) tgl gate width low 50 - 50 - 50 - ns 1 (23) tgs gate setup time to clk 50 - 40 - 40 - ns 1 (24) tgh gate hold time after clk 50 - 50 - 50 - ns 1 (25) tod output delay from clk - 150 - 100 - 100 ns 1 (26) todg output delay from gate - 120 - 100 - 100 ns 1 (27) two out delay from mode write - 260 - 240 - 240 ns 1 (28) twc clk delay for loading 0 55 0 55 0 55 ns 1 (29) twg gate delay for sampling -5 40 -5 40 -5 40 ns 1 (30) tcl clk setup for count latch -40 40 -40 40 -40 40 ns 1 note: 1. not tested, but characterized at initial design and at major process/design changes. 82c54
4-15 timing waveforms figure 17. write figure 18. read figure 19. recovery figure 20. clock and gate a0 - a1 cs data bus wr (12) tww (13) tdw (10) tsw (9) taw valid twd (14) twa (11) valid a0 - a1 cs rd data bus (2) tsr (6) tad (5) trd (4) trr (7) tdf tra (3) tar (1) (8) (15) trv rd, wr wr clk gate out mode count (see note) (17) tpwh (18) tpwl (16) tclk tgs (21) tgw (27) two tgs (23) tgh (24) tgl todg (26) tf (20) tod (25) tgh (24) note: last byte of count being written (19) tr (22) (23) tcl (30) twc (28) 82c54
4-16 burn-in circuits md 82c54 cerdip mr 82c54 clcc notes: 1. v cc = 5.5v 0.5v 2. gnd = 0v 3. vih = 4.5v 10% 4. vil = -0.2v to 0.4v 5. r1 = 47k w 5% 6. r2 = 1.0k w 5% 7. r3 = 2.7k w 5% 8. r4 = 1.8k w 5% 9. r5 = 1.2k w 5% 10. c1 = 0.01 m f min 11. f0 = 100khz 10% 12. f1 = f0/2, f2 = f1/2, ...f12 = f11/2 r1 r1 r1 r1 r1 r1 r1 r1 r2 r1 r1 r1 r1 r1 r2 r1 r1 r2 r1 vcc gnd q5 q4 a f1 q7 a q3 f2 q8 q2 vcc gnd f9 f11 f0 a q6 gnd q1 f10 f12 v cc a 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 v cc c1 r4 r3 23 24 25 22 21 20 19 11 3 2 1 4 14 15 16 17 18 12 13 28 27 26 10 5 6 7 8 9 vcc/2 q6 gnd open vcc/2 f1 q7 r1 r1 r1 r1 r2 r5 gnd q5 q4 q8 open f2 vcc/2 r1 r1 r1 r1 r1 r2 f9 f10 f11 open gnd f12 f0 r5 r1 r5 r1 r2 r1 r1 r1 r1 r1 vcc q2 q1 open c1 q3 vcc vcc 82c54
4-17 die characteristics die dimensions: 129mils x 155mils x 19mils (3270 m m x 3940 m m x 483 m m) metallization: type: si-al-cu thickness: metal 1: 8k ? 0.75k ? metal 2: 12k ? 1.0k ? glassivation: type: nitrox thickness: 10k ? 3.0k ? metallization mask layout 82c54 cs a1 a0 clk2 out2 gate2 d4 d3 d2 d1 d0 clk0 d5 d6 d7 vcc wr rd out0 gate0 gnd out1 gate1 clk1 82c54

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